Allo Documentation

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Paper

A Co-Design Compilation Flow as a Harness for Language Models to Improve It

Getting Started

Installation

Tutorials

Getting Started
Vivado/Vitis HLS Backend

Deep Dive

Frontend Syntax Guide
Dataflow Programming
Data Types and Type Casting
Template Kernels
Kernel Composition
IP Integration
PyTorch Integration
Equivalence Checking
Other Features

Backends

LLVM (CPU)
AMD Vitis HLS (FPGA)
Siemens Catapult HLS (FPGA)
SystemC emitter (Catapult, ASIC)
RapidStream TAPA (FPGA)
Google XLS (ASIC)
Multi-Threaded Simulator (CPU)
Non-Blocking Stream Operations
The ASIC manifest
AMD MLIR-AIE (AI Engine)

Accelerator Case Study

Tutorial: A PyTorch MLP on TinyTPU, Then Change It
TinyTPU-isa: A Programmable GEMM Accelerator
TinyTPU-isa: The ISA
TinyTPU-isa: Results and History
The Unit Library: Composing a Region from Units
The IP Library’s Gaps, and the Adder Tree
TinyTPU-isa vs Gemmini: A Matched Comparison
TinyTPU-isa vs Gemmini: Results and History
The Benchmark Set
The Workload Suite: PyTorch MLPs on TinyTPU
TinyTPU-isa: Design History
MiniTPU: Reference Architecture
Systolic-Array Design Space: Sourced Survey

Extensions

Catapult SystemC Flow and the Wire
CHIA Agentic Co-Design
CHIA Agentic Co-Design: Results
The Original Co-Design Effort (chia-codesign)
Agentic Experiments: What We Ran and What It Shows
ACT and the TinyTPU-isa Mapper
ACT Workload Specs and the Judge
ACT: Results, Findings and Corrections
The Co-design Loop: Mapping and Hardware Together

Developer Guide

Developer Setup
IR Builder Walkthrough
MLIR Translation Guide
Extending Allo’s Abstractions
Stream Ports: a Unit with an Interface
Actions: an Instruction as Composed Unit Effects
Allo Limitations Register
Dataflow Simulation Semantics: Allo vs HLS CSIM
Dataflow Region Pitfalls

Python API

Schedule Primitives
Data Types

Feature Details¶

Timing-based Profiling
Trace-based Profiling
User-Defined External Kernels

<Getting Started with MLIR-AIE

Timing-based Profiling>

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